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july 2006 rev 8 1/34 1 m24c64-w m24c64-r m24c64-f m24c32-w m24c32-r m24c32-f 64 kbit and 32 kbit serial i2c bus eeprom feature summary two-wire i 2 c serial interface supports 400khz protocol single supply voltage: ? 2.5 to 5.5v for m24cxx-w ? 1.8 to 5.5v for m24cxx-r ? 1.7 to 5.5v for m25cxx-f write control input byte and page write (up to 32 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection more than 1 million write cycles more than 40-year data retention pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mb) 2x3mm2 (mlp) www.st.com
contents m24cxx-w, m24cxx-r, m24cxx-f 2/34 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.2 internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 17 4.10 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m24cxx-w, m24cxx-r, m24cxx-f contents 3/34 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of tables m24cxx-w, m24cxx-r, m24cxx-f 4/34 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. operating conditions (m24cxx-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 8. operating conditions (m24cxx-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 9. operating conditions (m24cxx-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. dc characteristics (m24cxx-w6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. dc characteristics (m24cxx-w3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. dc characteristics (m24cxx-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. dc characteristics (m24c32-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. ac characteristics (m24cxx-w6 and m24cxx-w3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. ac characteristics (m24cxx-r, m24cxx-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. pdip8 ? 8 pin plastic dip, 0.25mm lead fram e, package mechanical data . . . . . . . . . . . . 27 table 19. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . 29 table 21. ufdfpn8 (mlp8) ? 8-lead ultra th in fine pitch dual flat package no lead 2 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
m24cxx-w, m24cxx-r, m24cxx-f list of figures 5/34 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. dip, so, tssop and ufdfpn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. maximum rp value versus bus parasitic capacitance (c) for an i2c bus . . . . . . . . . . . . . . 9 figure 5. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 10. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . . . . 27 figure 14. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . 28 figure 15. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
summary description m24cxx-w, m24cxx-r, m24cxx-f 6/34 1 summary description these i 2 c-compatible electrically erasable pr ogrammable memory (eeprom) devices are organized as 8192 8 bits (m24c64-x) and 4096 8 bits (m24c32-x). figure 1. logic diagram i 2 c uses a two-wire serial interface, comprising a bi-directional data line and a clock line. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in ta bl e 2 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. table 1. signal names e0, e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground ai01844c 3 e0-e2 sda v cc m24c64-w m24c64-r m24c64-f m24c32-w m24c32-r m24c32-f wc scl v ss
m24cxx-w, m24cxx-r, m24cxx-f summary description 7/34 figure 2. dip, so, tssop and ufdfpn connections 1. see package mechanical section for package dimensions , and how to identify pin-1. sda v ss scl wc e1 e0 v cc e2 ai01845d m24c64-x m24c32-x 1 2 3 4 8 7 6 5
signal description m24cxx-w, m24cxx-r, m24cxx-f 8/34 2 signal description 2.0.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.0.2 serial data (sda) this bi-directional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). 2.1 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code as shown in figure 3 . when not connected (left floating), these inputs are read as low (0,0,0). figure 3. device select code 2.2 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. when unconnected, the signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
m24cxx-w, m24cxx-r, m24cxx-f signal description 9/34 2.3 supply voltage (v cc ) 2.3.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 8 and ta b l e 9 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10nf to 100nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.3.2 internal device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 8 and ta b l e 9 ). when v cc has passed the por threshold, the device is reset and is in standby power mode. 2.3.3 power-down at power-down (continuous decrease of v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in the standby power mode (that is there should be no internal write cycle in progress). figure 4. maximum r p value versus bus parasitic capacitance (c) for an i 2 c bus ai01665b v cc c sda r p master r p scl c 100 0 4 8 12 16 20 c (pf) maximum rp value (k ? ) 10 1000 fc = 400khz fc = 100khz
signal description m24cxx-w, m24cxx-r, m24cxx-f 10/34 figure 5. i 2 c bus protocol table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1 0 1 0 e2 e1 e0 rw table 3. address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 table 4. address least significant byte b7 b6 b5 b4 b3 b2 b1 b0 scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
m24cxx-w, m24cxx-r, m24cxx-f memory organization 11/34 3 memory organization the memory is organized as shown in figure 6 . figure 6. block diagram ai06899 wc e1 e0 control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder scl sda e2
device operation m24cxx-w, m24cxx-r, m24cxx-f 12/34 4 device operation the device supports the i 2 c protocol. this is summarized in figure 5 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchroni zation. the m24cxx-w, m24cxx-r and m24cxx-f devices are always slaves in all communication. 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 4.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the stand-by mode. a stop condition at the end of a write command triggers the internal write cycle. 4.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 4.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
m24cxx-w, m24cxx-r, m24cxx-f device operation 13/34 4.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, t he bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit de vice type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into stand-by mode. table 5. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 s tart, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 32 start, device select, rw = 0
device operation m24cxx-w, m24cxx-r, m24cxx-f 14/34 figure 7. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120c page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
m24cxx-w, m24cxx-r, m24cxx-f device operation 15/34 4.6 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 8 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a period of time from the start condition until the end of the two address byte s) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 7 . each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte ( ta b l e 3 ) is sent first, followed by the least significant byte ( ta bl e 4 ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. 4.7 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 8 . 4.8 page write the page write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b12-b5 for m24c64-x, and b11-b5 for m24c32-x) are the same. if more bytes are sent than will fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (the 5 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition.
device operation m24cxx-w, m24cxx-r, m24cxx-f 16/34 figure 8. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106c page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
m24cxx-w, m24cxx-r, m24cxx-f device operation 17/34 figure 9. write cycle polling flowchart using ack 4.9 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in ta bl e 1 6 and ta bl e 1 7 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 9 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). ? step 2: if the device is busy with the internal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
device operation m24cxx-w, m24cxx-r, m24cxx-f 18/34 figure 10. read mode sequences 1. the seven most significant bits of the device select code of a random read (in the 1 st and 4 th bytes) must be identical. start dev sel * byte addr byte addr start dev sel data out 1 ai01105c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24cxx-w, m24cxx-r, m24cxx-f device operation 19/34 4.10 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device?s internal address counter is incremented by one, to point to the next byte address. 4.11 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 10 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 4.12 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 10 , without acknowledging the byte. 4.13 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 10 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 4.14 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its stand-by mode.
initial delivery state m24cxx-w, m24cxx-r, m24cxx-f 20/34 5 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 6 maximum rating stressing the device outside the ratings listed in ta bl e 6 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std- 020c (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c pdip-specific lead temperature during soldering 260 (2) 2. t lead max must not be applied for more than 10s. c v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (3) 3. aec-q100-002 (compliant wi th jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ) ?4000 4000 v
m24cxx-w, m24cxx-r, m24cxx-f dc and ac parameters 21/34 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 11. ac measurement i/o waveform table 7. operating conditions (m24cxx-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 8. operating conditions (m24cxx-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 9. operating conditions (m24cxx-f) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?20 85 c table 10. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
dc and ac parameters m24cxx-w, m24cxx-r, m24cxx-f 22/34 table 11. input parameters symbol parameter (1),(2) 1. t a = 25c, f = 400khz 2. sampled only, not 100% tested. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance v in < 0.3v cc 50 200 k ? z wch wc input impedance v in > 0.7v cc 500 k ? t ns pulse width ignored (input filter on scl and sda) 200 ns table 12. dc characteristics (m24cxx-w6) symbol parameter test condition (in addition to those in table 7 ) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) 2.5v < v cc < 5.5v, f c =400khz (rise/fall time < 30ns) 2ma i cc0 supply current (write) during t w , 2.5v < v cc < 5.5v 3 (1) 1. characterized value, not tested in production. ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 5.5v 5a stand-by supply current v in = v ss or v cc , v cc = 2.5v 2a v il input low voltage (sda, scl, wc ) ?0.45 0.3v cc v v ih input high voltage (sda, scl, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1ma, v cc = 2.5v or i ol = 3ma, v cc = 5.5v 0.4 v
m24cxx-w, m24cxx-r, m24cxx-f dc and ac parameters 23/34 table 13. dc characteristics (m24cxx-w3) symbol parameter test condition (in addition to those in table 7 ) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) 2.5v < v cc < 5.5v, f c =400khz (rise/fall time < 30ns) 2ma i cc0 supply current (write) during t w , 2.5v < v cc < 5.5v 3 (1) 1. characterized value, not tested in production. ma i cc1 stand-by supply current v in = v ss or v cc , 2.5v < v cc < 5.5v 10 a v il input low voltage (sda, scl, wc ) ?0.45 0.3v cc v v ih input high voltage (sda, scl, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1ma, v cc = 2.5v or i ol = 3ma, v cc = 5.5v 0.4 v table 14. dc characteristics (m24cxx-r) symbol parameter test condition (in addition to those in table 8 ) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) v cc =1.8v, f c = 400khz (rise/fall time < 30ns) 0.8 ma i cc0 supply current (write) during t w , 1.8v < v cc < 2.5v 3 (1) 1. characterized value, not tested in production. ma i cc1 stand-by supply current v in = v ss or v cc , 1.8v < v cc < 2.5v 1a v il input low voltage (sda, scl, wc ) ?0.45 0.3 v cc v v ih input high voltage (sda, scl, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 0.7 ma, v cc = 1.8 v 0.2 v
dc and ac parameters m24cxx-w, m24cxx-r, m24cxx-f 24/34 table 15. dc characteristics (m24c32-f) (1) 1. preliminary data. symbol parameter test condition (in addition to those in table 8 ) min. max. unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in stand-by mode 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) v cc =1.7v, f c = 400khz (rise/fall time < 30ns) 0.8 ma i cc0 supply current (write) during t w , 1.7v < v cc < 2.5v 3 (2) 2. characterized value, not tested in production. ma i cc1 stand-by supply current v in = v ss or v cc , 1.7v < v cc < 2.5v 1a v il input low voltage (sda, scl, wc ) ?0.45 0.3 v cc v v ih input high voltage (sda, scl, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 0.7 ma, v cc = 1.7 v 0.2 v
m24cxx-w, m24cxx-r, m24cxx-f dc and ac parameters 25/34 table 16. ac characteristics (m24cxx-w6 and m24cxx-w3) test conditions specified in table 10 and table 7 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (2) 2. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (3) 3. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 5 ms table 17. ac characteristics (m24cxx-r, m24cxx-f) test conditions specified in table 10 and table 8 or table 9 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (2) 2. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdx (3) 3. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 10 ms
dc and ac parameters m24cxx-w, m24cxx-r, m24cxx-f 26/34 figure 12. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
m24cxx-w, m24cxx-r, m24cxx-f package mechanical 27/34 8 package mechanical figure 13. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline 1. drawing is not to scale. table 18. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 ? ? 0.100 ? ? ea 7.62 ? ? 0.300 ? ? eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
package mechanical m24cxx-w, m24cxx-r, m24cxx-f 28/34 figure 14. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 19. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m24cxx-w, m24cxx-r, m24cxx-f package mechanical 29/34 figure 15. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 20. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
package mechanical m24cxx-w, m24cxx-r, m24cxx-f 30/34 figure 16. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline 1. drawing is not to scale. table 21. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.55 0.50 0.60 0.022 0.020 0.024 a1 0.00 0.05 0.000 0.002 b 0.25 0.20 0.30 0.010 0.008 0.012 d 2.00 0.079 d2 1.55 1.65 0.061 0.065 ddd 0.05 0.002 e 3.00 0.118 e2 0.15 0.25 0.006 0.010 e0.50? ?0.020? ? l 0.45 0.40 0.50 0.018 0.016 0.020 l1 0.15 0.006 l3 0.30 0.012 n8 8 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
m24cxx-w, m24cxx-r, m24cxx-f part numbering 31/34 9 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 22. ordering information scheme example: m24c32 ? w mn 6 t p /b device type m24 = i 2 c serial access eeprom device function 64 = 64 kbit (8192 x 8) 32 = 32 kbit (4096 x 8) operating voltage w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v f = v cc = 1.7 to 5.5v package bn = pdip8 mn = so8 (150 mil width) dw = tssop8 (169 mil width) mb = ufdfpn8 (mlp8) (1) 1. the ufdfpn8 package is available in m24c32-x devic es only. it is not avail able in m24c64-x devices. device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c 3 = automotive: device tested with high reliability certified flow (2) over ?40 to 125c. 2. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliability certified flow (hrcf) is des cribed in the quality note qnee9801. please ask your nearest st sales office for a copy. 5 = consumer: device tested with standard test flow over ?20 to 85c option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = ecopack? (rohs compliant) process b = f6dp26% rousset p = f6dp26% chartered
revision history m24cxx-w, m24cxx-r, m24cxx-f 32/34 10 revision history table 23. document revision history date revision changes 22-dec-1999 2.3 tssop8 package in place of tssop14 (pp 1, 2, orderinginfo, packagemechdata). 28-jun-2000 2.4 tssop8 package data corrected 31-oct-2000 2.5 references to temperature range 3 removed from ordering information voltage range -s added, and range -r removed from text and tables throughout. 20-apr-2001 2.6 lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated references to psdip changed to pdip and package mechanical data updated 16-jan-2002 2.7 test condition for i li made more precise, and value of i li for e2-e0 and wc added -r voltage range added 02-aug-2002 2.8 document reformatted using new template. tssop8 (3x3mm2 body size) package (msop8) added. 5ms write time offered for 5v and 2.5v devices 04-feb-2003 2.9 so8w package removed. -s voltage range removed 27-may-2003 2.10 tssop8 (3x3mm2 body size) package (msop8) removed 22-oct-2003 3.0 table of contents, and pb-free options added. minor wording changes in summary description, power-on reset, memory addressing, write operations, read operations. v il (min) improved to -0.45v. 01-jun-2004 4.0 absolute maximum ratings for v io (min) and v cc (min) improved. soldering temperature information clarified for rohs compliant devices. device grade clarified 04-nov-2004 5.0 product list summary table added. device grade 3 added. 4.5-5.5v range is not for new design. some minor wording changes. aec-q100- 002 compliance. t ns (max) changed. v il (min) is the same on all input pins of the device. z wcl changed. 05-jan-2005 6.0 ufdfpn8 package added. small text changes.
m24cxx-w, m24cxx-r, m24cxx-f revision history 33/34 29-jun-2006 7 document converted to new st template. m24c32 and m24c64 products (4.5 to 5.5v supply voltage) removed. m24c64 and m24c32 products (1.7 to 5.5v supply voltage) added. section 2.1: chip enable (e0, e1, e2) and section 2.2: write control (wc) modified, section 2.3: supply voltage (vcc) added and replaces power on reset: vcc lock-out write protect section. t a added, note 1 updated and t lead specified for pdip packages in table 6: absolute maximum ratings . i cc0 added, i cc voltage conditions changed and i cc1 specified over the whole voltage range in table 12: dc characteristics (m24cxx-w6) . i cc0 added, i cc frequency conditions changed and i cc1 specified over the whole voltage range in table 14: dc characteristics (m24cxx-r) . t w modified in table 16: ac characteristics (m24cxx-w6 and m24cxx- w3) . so8n package specifications updated (see figure 14 and ta bl e 1 9 ). device grade 5 added, b and p process letters added to ta b l e 2 2 : ordering information scheme . small text changes. 03-jul-2006 8 i cc1 modified in table 12: dc characteristics (m24cxx-w6) . note 1 added to table 15: dc characteristics (m24c32-f) and table title modified. table 23. document revision history (continued) date revision changes
m24cxx-w, m24cxx-r, m24cxx-f 34/34 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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